AI architecture and Performance Architect, CPU

Minimum qualifications:

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  
• 6 years of experience in the industry in high-performance CPU, DSP, AI architecture, microarchitecture, performance, or design.
  
• Experience in performance modeling, analysis, correlation, and workload characterization.
  
• Experience in C/C++ and scripting languages, e.g., Python.
  

Preferred qualifications:

• PhD in Electrical Engineering, Computer Engineering, or Computer Science, emphasizing on computer architecture or machine learning.
  
• Experience in leading CPU, DSP, or AI microarchitecture exploration, performance model development, performance analysis, and workload characterization.
  
• Knowledge with processor instruction set architecture (e.g., ARM, RISC-V, x86).
  
• Knowledge of system software components, such as Linux, drivers, and runtime.
  
• Ability to communicate in English fluently to communicate with US or EMEA teams.
  

About the job

As a CPU-AI architecture and performance architect, you'll be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and to deliver Google’s SoC products. You’ll have the opportunity to collaborate with talents in Google’s Android applications and Google’s AI teams to plan and conduct application and benchmark performance analysis and to project their performance at various design phases.

Responsibilities

• Plan and evaluate ARM’s architecture features from both architecture and performance angles.
  
• Develop a performance model for performance analysis and microarchitecture study.
  
• Define and write CPU-AI micro-architecture specifications.
  
• Lead collaborate with RTL,  design verification, and physical design teams to develop a high performance and efficient CPU-AI implementation.
  
• Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage.