ASIC AI/ML Design Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
  
• 2 years of experience with RTL design using Verilog/System Verilog and micro-architecture.
  
• Experience with ARM-based SoCs, interconnects, and ASIC methodology.
  

Preferred qualifications:

• Master’s degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
  
• 3 years of experience with IP design for clocking, interconnects, peripherals.
  
• Experience with methodologies for low-power estimation, timing closure, synthesis.
  
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
  

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Apply engineering best practices (e.g., code review, testing, refactoring) to the design and implementation of ASIC blocks.
  
• Write micro-architecture and own RTL implementation of key components and features.
  
• Engage with Verification and Silicon Validation teams to ensure functionality of design.
  
• Provide input on synthesis, timing closure, and Physical Design of digital blocks.
  
• Perform power, area, and performance trade-offs of digital designs and architectures.